An Integrated Circuit (IC) fabrication process involves forming electronic devices on a semiconductor substrate. A metal layer is deposited thereover and patterned to interconnect the semiconductor devices. The semiconductor devices and metal layer are then covered by dielectric materials such as silicon dioxide and spin-on-glass (SOG). The dielectric layer is etched back and then another layer of metal and dielectric materials are deposited thereover. This layering process continues to build the wafer until the IC is complete.
FIG. 1A depicts a cross section of a wafer 1 at an intermediate fabrication step. Wafer 1 is fabricated by forming electronic devices (not shown) on a semiconductor substrate 2, depositing a metal layer 3 thereover, and then patterning the metal layer 3 to interconnect the semiconductor devices. The height of the patterned metal layer results in an uneven topography. An oxide layer 4 is then deposited over the substrate and the metal layer. The oxide is typically a tetra-ethyl-orthosilicate (TEOS)-based oxide, deposited using chemical vapor deposition (CVD). The oxide layer forms hills in regions having metal thereunder and valleys in regions having no metal thereunder. This is simply a result of the underlying uneven topography. A thick SOG layer 5 is spun over the oxide layer and then etched back to planarize the uneven topography.
The SOG layer 5 must be etched back for two purposes: to provide a substantially planar surface for the deposition of additional materials; and to remove all the SOG from locations where vias through the oxide to the underlying metal will be placed, thus permitting a future metal deposition to fill the via and contact the underlying metal. Etching is a process known in the art and is typically performed using compounds such as CHF.sub.3, CF.sub.4, C.sub.2 F.sub.6 and combinations thereof.
Other planarization techniques include resist etchback, deposition-etch-deposition, and chemical mechanical polishing.
Surface planarity is an important figure of merit in integrated circuit fabrication. Planarity critically determines depth of focus during lithography, susceptibility to electrical shorts between interconnects, minimum overetch time to prevent residues and filaments, interconnect reliability, and structural stress induced in subsequently deposited films.
Referring to FIG. 1A, the desired etchback level is D. When the SOG layer and the oxide layer hills are etched back to level D, optimum IC characteristics are achieved. These characteristics include strong via construction, good planarity and controlled impedance between metal layers. The SOG etch rate and the oxide etch rate must be well matched during etchback to achieve good planarity.
FIG. 1A illustrates a poorly fabricated wafer 1 having a rough surface that will induce stress in subsequently deposited materials. FIG. 1B illustrates a properly fabricated wafer 10 having a smooth surface that will not induce stress in subsequently deposited materials.
Present testing techniques mostly test an IC after it has been completely fabricated. Testing techniques generally follow one of two philosophies: nondestructive testing that involves verifying the logical function of the IC; and destructive testing that involves dissecting the IC or subjecting the IC to excessive conditions to induce failure. Logic testing is beneficial because it verifies proper circuit operation. Dissection and maximum tolerance testing are beneficial because they offer information about the internal construction, durability and projected lifespan of the IC.
Present destructive tests include dissecting an IC and viewing it with a scanning electron microscope (SEM), scanning tunneling microscope (STM) or similar apparatus. Moreover, there are destructive tests for determining maximum thermal stress and voltage breakdown of an IC. The thermal stress test is destructive because it measures maximum thermal stress until the IC fails. The voltage breakdown test is destructive because it measures input voltage until the IC dielectric breaks down and the IC short circuits.
In traditional IC manufacturing, when a fabrication run is made, several thousand or more ICs are produced. From that fabrication run, many ICs are sampled out from the production and identified for destructive testing. The destructive test examples given above are typical of the tests performed. The rationale is that a statistical sample will demonstrate characteristics analogous to each of the ICs produced in the fabrication run.
Useful information is gained from a sampled IC by the following example. When a dissection test is performed, using a SEM for example, if the dielectric layers appear too thin, it indicates that the dielectric layers in the IC do not provide proper electromagnetic isolation between the conductors. It also indicates that there may be high stress in the thin layer. If the dielectric layers appear too thick, it indicates that the dielectric layers in the IC are Thicker than necessary to isolate the conductors. A thick dielectric layer also indicates that not enough dielectric material was etched back during fabrication. This results in weak via construction through unstable SOG material.
Destructive testing can only provide information about the devices tested. Thus, devices in the same fabrication run are assumed to be analogous to the sampled IC. The present invention discloses a method for obtaining similar information in a nondestructive way.
A drawback to present testing techniques is that testing is mostly performed after the IC fabrication is complete. This may result in unnecessarily finishing an IC that began to exhibit poor characteristics early in the fabrication process.
What is needed is a method of inspecting ICs during fabrication processing. By inspecting the wafers during intermediate IC fabrication steps, useful information can be obtained about the evolving wafer. Further, if these techniques are nondestructive, every wafer can be tested and those meeting test criteria can be sent on for further fabrication while those not meeting test criteria can be either discarded or sent back for remedial action. In addition, the manufacturing process for subsequent wafers can be adjusted to avoid the problems identified by the testing of earlier manufactured wafers. An inline nondestructive test directly promotes higher IC yield and longer IC life.
The present invention provides such a method.